With high integration of a semiconductor element and a reduction in chip size, finer wiring and multilayered wiring are acceleratingly promoted. In a logic device having such a multilayer wiring structure, wiring delay is becoming one of factors governing device signal delay. The device signal delay is proportional to the product of wiring resistance and wiring capacity, and hence, to improve wiring delay, reductions in wiring resistance and wiring capacity are important.
To reduce the wiring resistance, the formation of wiring with Cu which is low-resistance metal as a material is studied. Since it is very difficult to form wiring by patterning Cu, a so-called damascene method in which an opening which becomes a wiring trench or a connection hole (via hole) is formed in an insulating film and filled with Cu to form the wiring is worked out.
When Cu wiring is formed by the damascene method, a step of forming a base film which covers an inner wall of the opening before Cu is deposited is included, mainly in order to prevent Cu from diffusing into the insulating film. Refractory metal such as Ta or W used as a material for the base film is generally high resistant, but in recent years when finer wiring is promoted, it is indispensable to reduce the resistance value of the base film from a matter of wiring resistance. In particular, in the case of an ultra-fine wiring layer containing a via hole with a diameter of 0.1 μm and a wiring with a width of 0.1 μm, it is necessary to thin the base film as much as possible in order to reduce wiring resistance and contact resistance, and hence the technology for forming a base film thin and uniformly over an inner wall of a wiring trench or a via hole is desired.
A CVD method is first thought of as a method for forming such a base film. As far as the formation of the thin and uniform base film is concerned, it is thought that the use of the CVD method is advantageous, but the CVD method has a big problem in compatibility with and adhesiveness to a low dielectric constant insulating material which is expected as a material for the insulating film in which the opening is formed, and the application of this method is difficult in the present circumstances. A sputtering method is superior in the aforementioned compatibility and adhesiveness to the CVD method, whereby the use of the sputtering method for the formation of the base film is considered to be suitable.
At present, as sputtering technology used for forming the base film, there are a long throw sputtering method in which the distance between a substrate and a target is set longer than normal, a bias sputtering method in which a film is formed while a bias voltage is applied to a substrate, a multistep sputtering method in which two or more steps of sputtering as a combination of sputter deposition and sputter etching are performed, and so on.
However, under the present circumstances, even if the aforementioned various sputtering methods are used, the base film cannot be formed thin and uniformly over an inner wall surface, that is, from a side wall surface to a bottom surface, of the wiring trench or the via hole.
Specifically, part of a process of forming wiring containing a base film is shown in FIG. 1A to FIG. 3.
Here, for example, when a via hole 102 to connect a lower wiring 101 and an upper wiring not shown is formed in an interlayer insulating film 103 using an etching stopper film 104 and a hard mask 105, a Ta base film 106 is formed over the interlayer insulating film 103 so as to cover an inner wall of the via hole 102 by a sputtering method, and thereafter Cu 107 is deposited so as to be embedded in the via hole 102 by a plating method. Here, FIG. 1A shows a case where a long throw sputtering method is used as the sputtering method when the base film 106 is formed, FIG. 1B shows a case where a bias sputtering method is used, FIG. 2 shows a case where a multistep sputtering method (1) is used, and FIG. 3 shows a case where a multistep sputtering method (2) is used.
The Case of the Long Throw Sputtering Method
In the example of FIG. 1A, when a semiconductor substrate with a diameter of 200 mm is used, the method is carried out under the condition that the target power is between 10 kW and 20 kW, the pressure is 4×10−2 Pa, and the substrate bias power is between 0 W and 300 W. When a semiconductor substrate with a diameter of 300 mm is used, the method is carried out under the condition that the target power is between 20 kW and 40 kW, the pressure is 4×10−2 Pa, and the substrate bias power is between 0 W and 500 W.
In this case, Ta is thickly deposited over a bottom portion of the via hole 102 and a portion (field portion) other than the via hole 102 of the interlayer insulating film 103, whereas scarce Ta is deposited over a sidewall surface of the via hole 102, and as a result, due to insufficient coverage of the sidewall surface, poor embedding, for example, a void 108 occurs in the Cu 107 formed by plating.
The Case of the Bias Sputtering Method
In the example of FIG. 1B, when a semiconductor substrate with a diameter of 200 mm is used, the method is carried out under the condition that the target power is between 10 kW and 25 kW, the pressure is 4×10−2 Pa, and the substrate bias power is between 300 W and 600 W. When a semiconductor substrate with a diameter of 300 mm is used, the method is carried out under the condition that the target power is between 20 kW and 40 kW, the pressure is 4×10−2 Pa, and the substrate bias power is between 500 W and 1200 W.
In this case, excessive Ta is deposited not only over the bottom surface of the via hole 102 but also in the vicinity of a rim portion of the via hole 102 (a so-called overhang is formed). This causes poor embedding, for example, the void 108 on the side wall surface of the via hole 102 and a seam 109 in the vicinity of the entrance of the via hole 102 to the Cu 107.
The Case of the Multistep Sputtering Method (1)
In the example of FIG. 2, when a semiconductor substrate with a diameter of 200 mm is used, in a first step, long throw sputtering is carried out under the condition that the target power is between 10 kW and 25 kW, the pressure is 4×10−2 Pa, and the substrate bias power is between 0 W and 300 W, and in a second step, bias sputtering is carried out under the condition that the target power is between 10 kW and 25 kW, the pressure is 4×10−2 Pa, and the substrate bias power is between 300 W and 600 W. When a semiconductor substrate with a diameter of 300 mm is used, in a first step, long throw sputtering is carried out under the condition that the target power is between 20 kW and 40 kW, the pressure is 4×10−2 Pa, and the substrate bias power is between 0 W and 500 W, and in a second step, bias sputtering is carried out under the condition that the target power is between 20 kW and 40 kW, the pressure is 4×10−2 Pa, and the substrate bias power is between 500 W and 1200 W.
In this case, a portion over the bottom surface of the via hole 102 of the base film 106 is formed thick and the embedding property of Cu is relatively good, but an overhang caused by excessive deposition of Ta in the vicinity of the rim portion of the via hole 102 is formed, and thereby the thickness of the base film 106 becomes nonuniform.
The Case of the Multistep Sputtering Method (2)
In the example of FIG. 3, when a semiconductor substrate with a diameter of 200 mm is used, in a first step, long throw sputtering is carried out under the condition that the target power is between 10 kW and 25 kW, the pressure is 4×10−2 Pa, and the substrate bias power is between 0 W and 300 W, and in a second step, Ar resputtering is carried out under the condition that the target power is between 0.1 kW and 0.4 kW, the pressure is 4×10−2 Pa, and the substrate bias power is between 300 W and 600 W. When a semiconductor substrate with a diameter of 300 mm is used, in a first step, long throw sputtering is carried out under the condition that the target power is between 20 kW and 40 kW, the pressure is 4×10−2 Pa, and the substrate bias power is between 0 W and 500 W, and in a second step, Ar resputtering is carried out under the condition that the target power is between 0.1 kW and 0.5 kW, the pressure is 4×10−2 Pa, and the substrate bias power is between 500 W and 1200 W.
As shown by the arrows A, Ta deposited over the bottom surface of the via hole 102 in the first step adheres again to a side surface of the via hole 102 to make up a shortage of Ta over the side surface in the second step, but as shown by the arrow B, if an etching factor is strong, Ta becomes insufficient over the bottom surface of the via hole 102, which brings about a state in which hardly any Ta is deposited over the bottom surface. When positional displacement occurs between the lower wiring 101 and the via hole 102 due to this, for example, Cu deposited by plating diffuses into the interlayer insulating film 103. Furthermore, the seam 109 occurs in the vicinity of the entrance of the via hole 102 because of the formation of the overhang caused by the excessive deposition of Ta in the vicinity of the rim portion of the via hole 102.
The comparison of field portion film thicknesses, sidewall surface coverages, overhangs, via hole bottom surfaces, and embedding properties among the aforementioned long throw sputtering method, bias sputtering method, and multistep sputtering methods (1) and (2) will be shown in the following Table 1.
TABLE 1FieldFilmSidewallViaEmbeddingThicknessCoverageOverhangBottomPropertyLong ThrowThickThinSmallThickSidewallSputteringVoid Tendsto OccurOne-stepThickSlightlySlightlySlightlySeam/SideBiasThinLargeThinWall VoidsputteringOccurMultistepThickSlightlySlightlyThickRelativelysputteringThickLargeGood(1)EmbeddingMultistepThinThickLargeAlmostSeam TendsSputteringNothingto Occur(2)
Even if the various sputtering methods are used as just described, it is very difficult to form the basic film with a uniform film thickness in the opening. There is also a disadvantage that to control the film forming state of the base film, the multistep method with three or more steps needs to be adopted, which causes complication of a film forming process thereof, resulting in an increase in the time required for the process. This causes an increase in target power consumption, an increase in particles produced at the time of film formation, and a deterioration in throughput, which leads to a considerably thick deposition over the field portion while the necessary amount of film is formed in the opening. The base film deposited over the field portion needs to be removed by polishing in a chemical mechanical polishing (CMP) process, but the base film too thick leads to a deterioration in throughput in the CMP process and furthermore exerts a bad influence on the capability of the entire manufacturing line. Moreover, CMP of the base film has mechanical polishing as a strong factor, and hence flaws such as scratches tend to occur, which may contribute to a reduction in the yield of wiring formation.
(Patent Document 1)
Japanese Patent Application No. 2002-318674